1. Field of the Invention
This invention relates to computer systems and more particularly to computer systems having address translation with storage protection. The invention finds particular utility in computer systems where it is desirable to minimize the cost of the storage protection function and particularly where the programs in the computer system are independent of each other.
2. Prior Art
Heretofore it has been the practice to have discrete storage protection bits associated with a storage address to control the storage protection function. The storage protection bits were normally meaningful only when in the storage protection mode and could protect a storage location against being accessed for a read operation or written into for a write operation. The storage protection function could be independent of address translation. Prior art of this type is represented by U.S. Pat. No. 3,828,327. The present invention eliminates the need for having discrete storage protection bits associated with a storage address. Instead, the storage address is used to address a register which will contain either an address for allowing the storage operation to take place or an address which will generate a storage exception signal to inhibit the storage operation. Additionally, no boundary limits are required for the storage protection function as in U.S. Pat. Nos. 3,651,475, 3,742,458, and 3,827,029.
Also, in the past it has not been the practice to have separate address translation registers for CPU task operations and for I/O operations. For example, in U.S. Pat. No. 3,828,327 address translation was not provided for I/O operations. While address translation was available for both task and I/O operations in the computer system set forth on page 268 of the IBM Technical Disclosure Bulletin Vol. 19, No. 1, June 1976, only a single set of address translation registers were provided. Such an arrangement is more complex and could involve contention problems for the address translation registers between CPU tasks and I/O operations.
Also, in the past it has not been the practice to control the translate mode of operation based upon the current interrupt level or cycle steal. Also, it has not been the practice to have address translation control for a control processor independent of address translation control for a main storage processor.